This invention relates to semiconductor memory devices, and more particularly to a highly integrated random-access memory including a plurality of memory cells each made up of a transistor and a capacitor.
In the recent semiconductor field, need for increasing the memory capacity per chip causes progressive increase of integration density of the semiconductor memories. This trend is remarkable particularly in dynamic random-access memories (abbreviated as "dRAMs"). It may easily be understood that if the integration density is higher, it is more difficult to obtain a desired long data storage time of memory cells, because the capacitance of each memory cell capacitor decreases with increase of integration density. In the near future, the integration density of dRAMs will have 4 megabit (MB), 16 MB or more. In such dRAMs, even if a special grooved capacitor structure, called a "trench capacitor", is employed for the memory cell fabrication, the resultant memory cell capacitance is 40 fF at most. This fact implies that a desired long data storage time of the memory cells cannot be obtained.
The measure now taken for this data storage time problem is to increase the data refreshing cycle time of dRAMs. To complete the data refreshing with respect to all of the word lines, a 64 kilo-bit (KB) dRAM needs 128 data refreshing operations at the refreshing cycle of 2 ms. A 256 KB dRAM needs 256 data refreshings at the refreshing cycles of 4 ms. A 1 MB dRAM needs 512 data refreshing at 4 ms refreshing cycles. The increase of refreshing cycle time due to increase of the chip memory capacity allows the substantial data storage time of the memory cells to be long.
This approach, however, involves the problem of an unsatisfactory duty ratio of dRAMs. The problem arises from the fact that the increase of integration density of dRAMs is inevitably accompanied by the long refreshing time for all of the word lines. The term "duty ratio" of dRAMs means a ratio of the substantial access time to the entire operation time of dRAMs. This may also be defined as a difference value obtained by subtracting the refreshing or restoring time from the entire operation time. If the time necessary for refreshing all of the memory cells is long, the ratio of substantial data access time to the entire dRAM operation time, i.e., the duty ratio, is small. In actual use of dRAMs, there is a strong demand by user that the duty ratio of dRAM is set to values nearly equal to those of the current dRAM of normal integration density. The aforementioned approach cannot satisfy this user's demand.